1. Field of the Invention
The present invention relates to a semiconductor device and a data processing method.
2. Description of the Related Art
Recently, functions of devices that are demanded to have small areas and consume low amounts of power, such as mobile devices, are becoming more complicated and more diversified, and thus high performance is needed also for these devices. Manufacture and development of dedicated hardware is indispensable to successfully combine the high performance and downsizing and low power consumption. However, costs for manufacture and development of the dedicated hardware are increasing every year with the complexity and diversity of the functions. A semiconductor device that uses a dynamically reconfigurable circuit technology attracts attention as a device that can reduce the manufacture and development costs.
The semiconductor device that uses the dynamically reconfigurable circuit technology includes a reconfigurable circuit like a field programmable gate array (FPGA), and a storage device that stores therein plural pieces of circuit information required to configure a circuit to be executed in the reconfigurable circuit (hereinafter, simply “execution circuit”). This semiconductor device can configure an execution circuit by reading the circuit information required for an operation according to rules previously determined by software or the like. This semiconductor device is different from a typical semiconductor device that uses an FPGA in that the execution circuit can be changed during the operation.
When this semiconductor device is used, the development cost for dedicated hardware can be reduced like in the case of using an FPGA. Besides, various functions can be realized in the small semiconductor device by dynamically configuring the execution circuit. Therefore, reduction in the manufacture cost for dedicated hardware is also expected.
As examples of the semiconductor device that uses the dynamically reconfigurable circuit technology, there are a DRP (Dynamically Reconfigurable Processor, see “Reconfigurable System”, Ohmsha Ltd., pp. 189 to 194) of NEC Electronics Corporation, and ADRES (Architecture for Dynamically Reconfigurable Embedded System, see “Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes”, International Conference on Field Programmable Logic and Applications, pp. 106 to 111) of IMEC.
The DRP of NEC Electronics Corporation has a structure in which processing elements (PEs) as fundamental elements that execute calculations are arranged in a two-dimensional array, and a state transition controller is located at the center thereof. The PE is a calculating device capable of configuring an execution circuit, and plural pieces of circuit information including calculation types and connection relations between the PEs are stored in an instruction memory included in the PE. Each PE reads the circuit information from the instruction memory according to an instruction pointer provided by the state transition controller, and dynamically configures an execution circuit.
The state transition controller of the DRP enables simple state branching. The state transition controller determines a state of a branch destination based on an event signal transmitted from the PE array unit to the state transition controller. This system provides a mechanism of conditional execution in which, conditional upon results of calculations executed in the PE array, calculations to be executed next in the PE array are dynamically determined.
Meanwhile, the ADRES of IMEC has a structure in which reconfigurable cells (RCs) as fundamental elements that execute calculations are arranged in a two-dimensional array, and some of the RCs are coupled to a processor through a data register. The RC is a calculating device capable of configuring an execution circuit, and plural pieces of circuit information including calculation types and connection relations between the RCs are stored in a configuration memory included in the RC. The circuit information is read from the configuration memory by using an output of a configuration counter included in the RC as an address, and an execution circuit is dynamically configured.
The processor of the ADRES controls configuration of an execution circuit in the RC by initializing the configuration counter in the RC. The processor of the ADRES can read a result of a calculation executed by the RC through the data register. Accordingly, a mechanism of conditional execution can be realized in which, the configuration counter of the RC is initialized according to the read calculation result, thereby dynamically determining a calculation to be executed next in the RC conditional upon the calculation result from the RC.
The calculation executed in the RC supports predicate logics. Therefore, when different calculations are executed in different RCs and then only one calculation result is selected according to a predicate value calculated by another RC to set the selected result in the register of the RC, conditional executions in units of data can be also achieved.
To realize a high-performance semiconductor device that uses the dynamically reconfigurable circuit technology, the conditional execution in which, according to a result of a calculation executed by the semiconductor device, a calculation to be executed next is determined needs to be performed speedily.
However, because the DRP performs the conditional execution using the mechanism of state branching in the state transition controller, the conditional execution under a condition of different calculation results cannot be simultaneously performed in the PEs. Only the conditional execution under a condition of one calculation result can be performed in all the PEs.
In the mechanism of conditional execution using the predicate logics in the ADRES, many RCs are needed to perform one conditional execution while the conditional executions in units of data can be performed.
In the mechanism of conditional execution using the processor in the ADRES, a more complicated conditional execution than the conditional execution that uses a simple state branching mechanism in the DRP can be performed. However, because processing for determining, conditional upon a calculation result in the RC, a calculation to be executed next is determined is realized by the processor, time required for the conditional execution is longer than that required by the DRP.